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FEATURES Complete Analog Front End for ADSL Modems Part of ADI ADSL Chipset (AD20msp910) Designed to ANSI T1.413/ETSI TR238/ITU G.adsl Performance e.g., 6.1 Mbps Downstream Over 12K Ft. Suitable for CO or Residence (ATU-C and ATU-R) Includes Transmit and Receive Signal Paths: DAC: 20 MSPS 12-Bit Current Output ADC: 10 MSPS 12-Bit PGA: 0 dB-25 dB of Gain with 1 dB Steps Programmable Filters Auxiliary DAC for Timing Recovery Interface to 3.3 V or 5 V Digital Logic Low Power Consumption (485 mW) 80-Lead PQFP -40 C to +85 C Operation GENERAL DESCRIPTION
14 TX[13:0]
Analog Front End for ADSL AD6437
FUNCTIONAL BLOCK DIAGRAM
IOUT TXLPFIN 12-BIT DAC ANALOG FILTER TO DRIVER
3 CPORT
AD6437
CONTROL LOGIC ANALOG FILTER
LOOPBACK
PGA
VCXO 12 RX[11:0]
7-BIT DAC
FROM HYBRID
12-BIT ADC
RX_ADC
LOW PASS FILTER OUT
The AD6437 is a complete analog front-end IC (AD6437) for ADSL systems. Although part of the Analog Devices DMT chipset, it is suitable for use with digital implementations from other suppliers. As part of the AD20msp910 chipset, it complements the AD6435, the AD6436 and ADSP-2183; together with the AD816 driver and an external filter, they make a complete ADSL datapump, designed to comply with ANSI and ETSI standards for DMT-based ADSL.
The AD6437 includes both transmit and receive paths. These include the DAC (up to 20 MSPS, allowing for oversampling of the downstream transmit signal), ADC (up to 10 MSPS), low noise PGA and filters. The filters are software configurable for both the CO and RT modes. There is an auxiliary 7-bit auxiliary DAC (e.g., for timing recovery). The AD6437 has been designed to be versatile, and most blocks can be used or externally bypassed.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
This Material Copyrighted By Its Respective Manufacturer
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997
AD6437-SPECIFICATIONS
Parameter TRANSMIT CHANNEL SNR THD DAC Resolution Sample Rate Data Format Output Compliance Range TRANSMIT FILTER Input Voltage Range Input Impedance Output Voltage Range CO Mode 3 dB Frequency Stopband Rejection @ 16 MHz Passband Passband Gain RT Mode 3 dB Frequency Stopband Rejection @ 2.07 MHz Passband Passband Gain RECEIVE CHANNEL SNR THD PGA Gain Range Gain Error Gain Step Error Input Resistance Input Voltage Range Input Referred Noise Output Voltage Range ADC Resolution Sample Rate Data Format Input Voltage RECEIVE FILTER 3 dB Frequency Stopband Rejection @ 16 MHz Pass Band Gain Input Voltage Range Output Voltage Range CONTROL Timing Recovery DAC Resolution Sample Rate Output: Low Output: High Data Format Min Typ 70 72 12 20 2.0 2.0 10 2.0 4 26 1.1 0.5 600 25 138 0.5 70 72 0-30 1 0.25 500 5 12 5 12 10 5 4 53 0.5 5 5 Max Units dB dB Bits MSPS V ppd 4th Order Butterworth V ppd k V ppd MHz dB MHz dB kHz dB kHz dB dB dB dB dB dB V ppd nV/Hz V ppd Bit MSPS V ppd 4th Order Butterworth MHz dB dB V ppd V ppd Passband 0 MHz-1.1 MHz 400 kHz Test Tone, First Five Harmonics 0.5 dB Below fS Out Ohms Differential Load Impedance 30 k|30 pF Notes 400 kHz Test Tone, First Five Harmonics
Guaranteed by Design Straight Binary
30% Differential 25 dB Gain, 1.2 MHz
Guaranteed by Design Straight Binary
7 770 0.5 4.5
Bit kHz V V
Monotonic Guaranteed by Design Sink/Source 50 A max Sink/Source 50 A max Straight Binary
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AD6437
Parameter DIGITAL INTERFACE Input Levels Output Levels Serial Interface: Clock Rate ELECTRICAL Analog Power Supply (AVDD) 3 V Digital Power Supply (DVDD_3) 5 V Digital Power Supply (DVDD_5) IDVDD 5 V IDVDD 3 V IAVDD Power Consumption (Normal) Power Consumption (Low Power)
Specifications subject to change without notice.
Min
Typ
Max
Units
Notes 3.3 V or 5 V Compatible 3.3 V or 5 V Compatible Guaranteed by Design
10 4.75 3.00 4.75 5.0 5.0 13 0.1 84 485 266 5.25 3.3 5.25
MHz V V V mA mA mA mW mW
600
Reg B Bit 4 Set
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6.0 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Operating Temperature Range (Ambient) . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model
Temperature Range
Package Description Plastic Quad Flatpack
Package Option S-80A
AD6437 -40C to +85C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6437 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS Pin Number 1, 24, 64 2, 25, 63, 71 3, 72 4-6, 21, 22, 26, 40, 44, 55, 56, 61, 80 7-20 23 27 28, 29 30, 31 32, 39, 54 33, 38, 53 34, 35 36, 37 41, 42 43, 45 46, 47 48 49 50, 51 52 57 58 59 60 62 65-70, 73-78 79 Pin Name DVDD_5 V DGND DVDD_3 V NC TX[13:0] TX_CLK TX_FSADJ TX_COMP, TX_IBIAS TX_DACOUT[A, B] AGND AVDD TX_FILIN[A, B] TX_FILOUT[B, A] RX_PGA_IN[B, A] RX_AAF_OUT[B, A] RX_ADC_IN[A, B] RX_VREF RX_REFGND RX_REFB, RX_REFT RX_CML TR_DAC_OUT SFRAME SCLK SDATA TEST RX[0:11] RX CLK Description +5 V Digital Supply for Converters. Must be connected to 5 V. Digital Ground. Digital Supply for Interface. Can be connected to 3.3 V or 5 V to suit different digital circuitry. No Connect. Digital Transmit Data to DAC. DAC Clock Input Data Latched on Positive Edge. Resistor to AGND from this pin sets the full-scale transmit DAC current output. Decoupling Pins for Internal Nodes. Complementary Current Outputs. Analog Ground. +5 V Analog Supply. Differential Input to Transmit LPF. Differential Output from Transmit LPF. Differential Input to PGA. Differential Output of Antialias Filter. Differential Input to ADC. External Voltage Reference Output. External Voltage Reference Ground. Decoupling Pins for ADC Reference Voltage. Common-Mode Level. Nominally half the supply voltage. Voltage Output from Timing Recovery DAC. Frame Sync for Timing Recovery DAC Data. Clock for Timing Recovery DAC Serial Data. Serial Data Input to Timing Recovery DAC. Factory Test Digital Output (Receive) Data from ADC. ADC Clock Input Sampled on Positive Edge. PIN CONFIGURATION
DVDD_3V RXCLK DVDD_5V DGND DGND
RX11
RX10
RX5
RX4
RX3
RX2
RX1
TEST
RX9
RX8
RX7
RX6
RX0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVDD_5V 1 DGND 2 DVDD_3V 3 NC 4 NC 5 NC 6 TX13 7 TX12 8 TX11 9 TX10 10 TX9 11 TX8 12 TX7 13 TX6 14 TX5 15 TX4 16 TX3 17 TX2 18 TX1 19 TX0 20
NC
NC
60 SDATA 59 SCLK 58 SFRAME 57 TR_DAC_OUT 56 NC 55 NC 54 AGND 53 AVDD 52 RX_CML 51 RX_REFT 50 RX_REFB 49 RX_REFGND 48 RX_VREF 47 RX_ADCINB 46 RX_ADCINA 45 RX_AAF_OUTA 44 NC 43 RX_AAFOUTB 42 RX_PGA_INA 41 RX_PGA_INB
PIN 1 IDENTIFIER
AD6437
TOP VIEW (Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
TX_DACOUTA
TX_FILOUTA
TX_COMP
NC
TX_FSADJ
DVDD_5V
AGND
DGND
TX_CLK
TX_IBIAS
TX_DACOUTB
TX_FILOUTB
AGND
AVDD
AVDD
NC
NC
NC = NO CONNECT
TX_FILINA
TX_FILINB
NC
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CIRCUIT DESCRIPTION
GENERAL
full-scale. The full-scale output current of the DAC is set through an external resistor. The relationship is: IOUT_ full-scale = 40/RSET Amps e.g., RSET is 2 k for a 20 mA full-scale output. The current can be converted to a voltage by a grounded resistor. Ideally, this would be immediately converted to a large signal to preserve SNR. However, the output compliance of the DAC is 1.0 V. The resistors would be chosen to be <49.9 for a 1.0 V output (2 V ppd) to stay within the compliance range. The power consumption of the AD6437 can be reduced by lowering IOUT_full-scale. Lowering the full-scale current does increase the THD of the DAC outputs. Lowering the output current would require the termination resistors to increase by the same ratio to maintain a 2 V ppd output signal. This, however, will in turn raise the source impedance.
The AD6437 is designed as the analog front end for the AD20msp910 chipset or other ADSL systems. The AD6437 contains programmable filters that make it suitable for both ATU-C and ATU-R modem applications. Many of the internal circuit of the AD6437 can be programmed or bypassed, making it a versatile CODEC that can be used in other ADSL applications or instrumentation and control systems. There are four major sections to the AD6437: the transmit channel, which contains a 12-bit DAC and a fourth order reconstruction filter; the receive channel, which includes a PGA with 30 dB of dynamic range, a fourth order antialiasing filter and a 12-bit, 10 MSPS ADC; auxiliary and support circuitry, which consists of a 7-bit DAC used for timing recovery and analog switches used for bypassing internal blocks and channel loopback; finally, there is the interface and control logic. The AD6437 core runs from a single 5 V supply. The digital interface circuitry can run from either a 3.3 V or 5 V supply. All the analog input and output signals are processed in a fully differential mode. This affords greater immunity to externally coupled noise as well greater signal swings throughout the signal path.
TRANSMIT CHANNEL
AD6437
TX_DACOUTB TX_DACOUTA TX_FSADJ TX_IBIAS TX_COMP TX_FILINA TX_FILINB
RSET 2k
CA 0.1 F
The data is received from the digital section (e.g., the AD6436 DME) in parallel format, and passed to the DAC. The output from this is available externally in complementary voltage (TX_DACOUTA, B). Typically, it will then be connected to TXLPF for the on-chip reconstruction filter (4th order Butterworth active filter). However, this filter can be bypassed if a different filter is required (e.g., to use the AD6437 in a nonstandard application). The filter can be switched between two corner frequencies, for use in CO mode or RT mode. For downstream operation (CO mode), the band ends at 1.1 MHz and the filter's 3 dB corner is set at 4 MHz. For upstream operation (RT mode), it is set to 600 kHz, with flat response (0.5 dB guaranteed) up to 138 kHz. The selection is made by the txfsel bit in Control Register D (Bit 0).
DAC Output
CB 0.1 F RB 49.9 RA 49.9
CTA 0.1 F
AVDD AGND SHORTEST CONNECTION TO GROUND
CTB 0.1 F
Figure 1. Typical Configuration: Transmit Path
Tx LPF
The AD6437 Tx low-pass filter is designed to attenuate the images created at the DAC output due to the sampling process. The amount of attenuation required is specified in the ANSI T1.413 specification in Sections 6.12 and 7.12 for the ATU-C and ATU-R respectively. The AD6437 filter is designed to meet or exceed these requirements. The AD6437 Tx LPF is implemented as a fully differential 4th order Butterworth filter. The input voltage range is 2 V ppd, centered about 2.5 volts. The input impedance is approximately 10 k differential. The passband gain of the filter is unity. The THD of the filter is typically less than -75 dB when driving a 30 k|30 pF load. However, the THD rises as the load impedance is decreased. As a result, the load impedance driven by the filter should be kept as high as possible.
The DAC is a 12-bit differential output current DAC. The digital coding is straight binary. When the digital inputs are all 1s, IOUTA is at full scale. The value of the outputs are complimentary (i.e.,--when IOUTA is at full scale, the current from IOUTB is zero). The current outputs are nominally set to 20 mA
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AD6437
RECEIVE CHANNEL Table I. Programmable Gain Amplifier Control
The receive channel consists of the programmable gain amplifier, antialias filter and ADC.
Programmable Gain Amplifier
The input from hybrid and filters is required to drive the PGA input. This is centered at 2.5 V and has a maximum input voltage range of 5 V ppd. The input impedance is low, 500 (differential) 30%. This means that the amplifier must be able to drive a low impedance with low THD up to 1.1 MHz. Additionally, the multiple feedback topology requires that the amplifier be voltage feedback. Also, the input referred noise should be as low as possible to preserve the SNR of the channel.
Receive Filters
Pg 5 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Pg 4 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Pg 3 x 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Pg 2 x x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Pg 1 x x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Pg 0 x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Relative Gain (dB) 0 0 0 1 2 3 4 5 6 6 6 7 8 9 10 11 12 12 12 13 14 15 16 17 18 18 18 19 20 21 22 23 24 24 24 25 26 27 28 29 30 30
The antialias filter is set to a 3 dB corner at 4 MHz. If desired, the filter can be bypassed and an external one used instead.
Analog-to-Digital Converter
The analog-to-digital converter operates to 12-bit resolution (11-bit linearity), and is clocked at up to 10 MHz. The filter capacitors shown in Figure 2 are used to decouple the internal reference voltages of the ADC. A buffer is required after the filters, at the input to the ADC. This must be able to drive the 30 pF input capacitance of the ADC, with the desired bandwidth and distortion properties. A typical part is the AD8042.
RX_AAFOUTA
RX_AAFOUTB
AD6437
RX_REFB RX_VREF RX_REFT RX_CML
0.1 F 0.1 F 10 F 10 F 0.1 F
0.1 F
0.1 F 15k
15k 10 10
0.1 F 0.1 F
2.5V
AD8042
15k
15k
Figure 2. Typical Configuration: Receive Path
ADDR 0 LSB 2 REG SELECT 3 4 5 DATA 12 MSB
TRANSMITTED LSB FIRST
Figure 3. Serial Data Format
RX_ADCINB
RX_ADCINA
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ANCILLARY AND SUPPORT SECTION Auxiliary D/A SERIAL INTERFACE
There is a 7-bit monotonic DAC, with an output buffer, that can be used for system control. Typically, this will be used for timing recovery, to drive a VCXO. The output buffer load must be greater than 100 k.
DIGITAL INTERFACE TO AD6437
The serial port interface has the ability to interface with most digital systems (e.g., the ADSP-2183 used in the Analog Devices ADSL chipsets). The interface consists of three signals: SDATA, SCLK and SFRAME (described in Table II and Figure 6). The SDATA and SFRAME are clocked into the DSP Interface block on a falling edge of SCLK. The DSP interface decodes the first three bits of the incoming data word to determine if the AD6437 is being addressed. If the DSP has selected the AD6437, the next 10 bits are accepted. The first two bits decode one of four internal data registers (Reg A, Reg B, Reg C, and Reg D), and the following eight bits used as data to be loaded into that register. NOTE: The AD6437 registers may not start up in a defined state on power-up. They should be cleared to explicitly set them to a known state before use.
The digital I/O pins can interface to either 3.3 V or 5 V logic. The voltage connected to the DVDD_3 V power pins (Pins 3 and 72) determines the interface voltage. Although the DVDD_3 V pins can be connected to either 3.3 V or 5 V, they must be connected to the same voltage. When interfacing to the other chips in the ADSL system, the AD6437 DVDD_3 V power pins should ideally be connected to 3.3 V; in addition to lower power consumption, this lowers board noise and digital feedthrough into the AD6437 data converters. DVDD_5 V must always be connected to 5 V. See the Digital Interface section of the electrical specifications in the AD6437 data sheet for details on minimum and maximum logic levels.
Table II. AD6437 Serial Port I/O
Pin Name SDATA SFRAME SCLK
Definition Data Transmit Transmit Frame Sync Serial Clock
Type Input Input Input
Description Data Output from Host Processor (e.g., ADSP-2183) Sync Output from Host Processor Clock Output from Host Processor
Table III. Register Function
Register REG A REG B REG C REG D PGA Control Power Mode Aux DAC Data Control
Bit 7 NA NA NA test1
Bit 6 NA NA trd6 NA
Bit 5 Pg 5 NA trd5 NA
Bit 4 Pg 4 lpchip trd4 test
Bit 3 Pg 3 pdpgaaa trd3 NA
Bit 2 Pg 2 pdtxfil trd2 alpbk
Bit 1 Pg 1 pdtrdac trd1 aafbp
Bit 0 Pg 0 pd12dac trd0 txfsel
NA = Not Assigned.
Table IV. Register Bit Field Function
Name Pg[5:0] lpchip pdpgaaa pdtxfil pdtrdac pd12dac trd[6:0] alpbk aafbp txfsel
Field Reg A Reg B[4] Reg B[3] Reg B[2] Reg B[1] Reg B[0] Reg C Reg D[2] Reg D[1] Reg D[0]
Description Programmable Gain Amplifier Gain Bits. Pg 0 LSB. See Table I. Low Power Mode. Powers down all chips except ADC. Active High. Power-Down Receive PGA and AA Filter. Active High. Power-Down Transmit Filters. Active High. Power-Down Timing Recovery DAC. Active High. Power-Down 12-Bit DAC. Active High. Timing Recovery DAC Data; trd0 LSB, Data Format Binary. Analog Loop Back. Active High. AA Filter Bypass. Active High. Powers down the filter. Transmit Filter Select. txfsel = 0, 138 kHz, txfsel = 1, 1 MHz Filter Select.
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Table V. Serial Interface Data Format
SDATA [2:0] Determines if AD6437 is selected, Addr 101 is assigned for AD6437.
SDATA [3:4] Selects AD6437 register. SDATA [4 3] 0 0 Reg A 0 1 Reg B 1 0 Reg C 1 1 Reg D
SDATA [5:12] Data byte written (LSB first). SDATA 12, MSB SDATA 5, LSB
NOTE Data is transmitted in 13-bit words: SDATA 0, LSB, transmitted first; SDATA 12, MSB, transmitted last.
TIMING
TX[13:0]
tS
TXCLK
tH
t LPW
Figure 4. Transmit DAC Data Timing
Table VI. Transmit DAC Timing
Symbol tS tH tLPW
Min 12 12 16
Typ Max
Units ns ns ns
RECEIVE INTERFACE
The analog input is sampled every the rising edge of the ADC clock (RX_CLK), with digital data (RX11:RX0) being valid on each falling edge of RX_CLK. Due to the pipeline architecture used in the ADC, there is a three-cycle latency in the receive data as shown in the diagram.
S1 ANALOG INPUT S2 S4 S3
tC t CH t CL
INPUT CLOCK RCVCK
t OD
OUTPUT DATA RX[0:11] DATA1
Figure 5. Receive Interface Timing Diagram
Table VII. Receive Switching Specifications
Symbol tC tCH tCL tOD Latency
Parameter Clock Period CLOCK Pulsewidth High CLOCK Pulsewidth Low Output Delay Pipeline Delay
Min 45 45 8 3
Typ 100
Max
Units ns ns ns ns Cycles
13 3
19 3
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DRIVE EDGE SAMPLE EDGE
t SCLKW
SCLK
t RD
SFRAME
t RH
t SCDV
SDATA_IN VALID DATA
t SCDH
Figure 6. Serial Port Interface Timing
SIMPLEX DATA DUPLEX DATA
AD6435
(DTIR)
AD6436
(DME)
AD6437 (AD6437) AD8042
(BPF) HYBRID
TO LINE AND POTS SPLITTER
AD816
(DRIVER/ RECEIVER)
TO RAM (INTERLEAVE) CONTROL MESSAGES
AD826
BUFFER
ADSP-2183
TO BOOT EPROM
Figure 7. Example System Configuration
Table VIII. Serial Port Interface Timing Parameters
Symbol tSCLKW tRD tRH tSCDV tSCDH
External Clock Switching Characteristics Clock Period (6.6 MHz) SFRAME Delay After SCLK SFRAME Hold After SCLK SCLK High to SDATA Valid (Delayed) Transmit Data Hold After SCLK
Typ 151
Min
Max 15
Units ns ns ns ns ns
0 15 0
Typical 6.6 MHz synchronous control interface rate.
CONNECTION AND APPLICATION INFORMATION Decoupling
All the internal bias points of the AD6437 DAC and ADC are decoupled as shown in Figures 2 and 3. All AD6437 power pins should be decoupled with a 10 F tantalum capacitor and a parallel 0.1 F ceramic chip cap. The 0.1 F capacitors should be placed as closely as possible to the device pins. This configuration ensures a low impedance power source over a wide band of frequencies.
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AD6437
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead Plastic Quad Flatpack (PQFP) (S-80A)
0.134 (3.40) MAX 0.041 (1.03) 0.029 (0.73) SEATING PLANE
0.690 (17.45) 0.667 (16.95) 0.555 (14.10) 0.547 (13.90) 0.486 (12.35) BSC
80 1 61 60
0.486 (12.35) BSC 0.555 (14.10) 0.547 (13.90)
41 40
TOP VIEW
(PINS DOWN)
0.004 (0.10) MAX 0.010 (0.25) MIN 0.120 (3.05) 0.100 (2.55)
20 21
0.026 (0.65) BSC
0.015 (0.38) 0.009 (0.22)
0.690 (17.45 0.667 (16.95)
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PRINTED IN U.S.A.
C3228-3-10/97

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